Instruction Formats in Computer Organization:- Computers may have instructions of several different lengths containing varying numbers of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.
Instruction Formats in Computer Organization
In this post, we discuss Instruction Formats in Computer Organization. Based on the number of addresses, instructions are classified as:
A stack-organized computer does not use an address field for the instructions. ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The following program shows how X= (A + B)*(C+ D) will be written for a stack-organized computer. (TOS stands for top of stack).
PUSH A TOS <- A
PUSH B TOS <- B
ADD TOS <- (A+ B)
PUSH C TOS <- C
PUSH D TOS <- D
ADD TOS <- (C+ D)
MUL TOS <- (C+D)*(A + B)
POP X M[X] <- TOS
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse Polish notation. The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions.
One-address instructions use an implied accumulator (AC) register for all data manipulation. For multiplication and division, there is a need for a second register. However, here we will neglect the second register and assume that the AC contains the result of all operations. The program to evaluate X= (A + B) (C+ D) is
LOAD A AC <- M[A]
ADD B AC <- AC + M[B]
STORE T M[T] <- AC
LOAD C AC <- M[C]
ADD D AC <- AC+M[D]
MUL T AC <- AC*M[T]
STORE X M[X] <- AC
All operations are done between the AC register and a memory operand. T’ is the address of a temporary memory location required for storing the intermediate result.
Two-address instructions are the most common in commercial computers. Here again, each address field can specify either a processor register or a memory word. The program to evaluate X= (A + B) (C+D) is as follows:
MOV R1, A R1 <- M[A]
ADD R1, B R1 <- R1 + M[B]
MOV R2, C R2 <- M[C]
ADD R2, D R2 <- R2 + M[D]
MUL R1, R2 R1 <- R1*R2
MOV X, R1 M[X] <- R1
The MOV instruction moves or transfers the operands to and from memory and processor registers. The first symbol listed in instruction is assumed to be both a source and the destination where the result of the operation is transferred.
Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand. The program in assembly language that evaluates X-(A+B)(C+ D) is shown below, together with comments that explain the register transfer operation of each instruction.
ADD R1, A, B R1 <- M[A] + M[B]
ADD R2, C, D R2 <- M[C]+M[D]
MUL X, R1, R2 M[X] <- R1*R2
It is assumed that the computer has two processor registers, R1 and R2. The symbol M denotes the operand at memory address symbolized by A. The advantage of the three-address format is that it results in short programs when evaluating arithmetic expressions. The disadvantage is that the binary-coded instructions require too many bits to specify three addresses. An example of a commercial computer that uses three-address instructions is the Cyber 170. The instruction formats in the Cyber computer are restricted to either three register address fields or two register address fields and one memory address field.